vmx: Fix bug in VMX VPMU fixed function PMC offset

This is a minor fix to the calculation of bit-width of fixed function
perfmon counters in Intel processors.  Bits 5-12 of edx register
should be calculated as (edx & 0x1fe0) >>5 instead of using 0x1f70.

From: "John, Jaiber J" <jaiber.j.john@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>

diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 4646600ca4191875681466b26e38d21ec3999f86..ce4fd2d43e04db5e9b042344dd294cfa11e1f405 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -83,7 +83,7 @@ static int core2_get_bitwidth_fix_count(void)
 {
     u32 eax, ebx, ecx, edx;
     cpuid(0xa, &eax, &ebx, &ecx, &edx);
-    return ((edx & 0x1f70) >> 5);
+    return ((edx & 0x1fe0) >> 5);
 }
 
 static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)